1. Field of the Invention
This invention relates generally to an improved method for fabricating double-diffused MOS (DMOS) transistors and, more particularly, to an improved method of fabricating DMOS power transistors that can be used either in a discrete or an integrated structure or format.
2. Description of the Prior Art
In the past, DMOS transistors have been utilized either as discrete power transistors or as components in monolithic integrated circuits. DMOS transistors are inherently conservative of semiconductor ("real estate") substrate area because of the manner in which they are fabricated in a self-aligned fabrication sequence.
A channel body region was usually first formed by dopant introduction of one type dopant (P or N impurities) through an aperture in a mask of gate-forming material to provide a channel region which was self-aligned with the gate. Then a source region was usually formed by dopant introduction of a type opposite to that of the channel body region through the existing aperture so that the source was self-aligned to both the gate electrode and the channel body region. This permitted a very compact structure that utilized very little semiconductor "real estate."
However, in most applications of the DMOS device, particularly for power devices, it is necessary to form a very low-resistance electrical short between the channel body region and the source region to prevent undesired parasitic transistor action that might occur without shorting the body region to the source region. Because the channel body region is lightly doped, and because a low resistance electrical contact to a semiconductor region typically requires a heavily-doped surface region, it is necessary to provide an auxiliary heavily doped contact region for the channel body region to insure a good electrical contact to both the source and body regions. Such a heavily doped body region usually could not be self-aligned and hence there was an increase in the overall size of the DMOS device. Typically, the heavily doped body contact region was usually formed before the other two regions. Then a rather thick masking oxide patterned layer was used to protect the heavily doped body contact region against the source region dopant introduction step. The necessity to etch away or remove this masking oxide patterned layer together with any oxide over the source regions without disturbing the insulator over and/or under the gate electrode increased costs, tolerances, and process complexity and, as a result, decreased the yields of electrically good devices.
While various processes have been utilized in an attempt to ameliorate the foregoing problem, a need existed to provide an improved DMOS fabrication method and process sequence which allows an effective source to channel body electrical short without decreasing yield and which permits or is susceptible to device dimensional reduction.